A data transfer method which has a plurality of FIFO memories storing each of a plurality of divided data transferred in parallel is known (refer to Patent Document 1). A timing instruction unit monitors a data storage state of each of the plurality of FIFO memories, and outputs a timing signal instructing reading of data when the data are stored at all of the FIFO memories. A plurality of holding units are provided to correspond to each of the plurality of FIFO memories, and download and hold the divided data stored at the plurality of FIFO memories in synchronization with the timing signal output from the timing instruction unit.
Besides, a skew correction circuit which has a detection unit detecting an edge of one transmission signal from among edges to be the same timing among a plurality of transmission signals transmitting parallel transmission paths is known (refer to Patent Document 2). A correction signal generation unit generates a correction signal in accordance with a cycle of the edge detected by the detection unit. A correction unit outputs the edges of the plurality of transmission signals with each other in synchronization with the correction signal generated at the correction signal generation unit.
Besides, a semiconductor device which has an input circuit downloading a plurality of data from outside in synchronization with a plurality of clock signals from outside is known (refer to Patent Document 3). A pulse signal generation circuit generates a pulse signal. A drive circuit supplies the plurality of data which are downloaded by the input circuit to an internal circuit while aligning at the same timing in accordance with a timing of the pulse signal.
Besides, an asynchronous transmission device which receives at least one notification signal which is transmitted in accordance with a transmission clock in accordance with a reception clock, is known (refer to Patent Document 4). A trigger signal transmission part outputs a trigger signal based on a symbol cycle of the notification signal. A notification signal transmission part outputs the notification signal whose timing is shifted for a predetermined time relative to a timing of the trigger signal output by the trigger signal transmission part. A trigger signal synchronization part receives the trigger signal output from the trigger signal transmission part to synchronize the trigger signal, and outputs a sampling timing signal which indicates a sampling timing of the notification signal which is output from the notification signal transmission part. A notification signal holding part holds the notification signal which is received from the notification signal transmission part in accordance with the sampling timing signal.
[Patent Document 1] Japanese Laid-open Patent Publication No. H10-247175
[Patent Document 2] Japanese Laid-open Patent Publication No. H6-54016
[Patent Document 3] Japanese Laid-open Patent Publication No. 2003-85130
[Patent Document 4] Japanese Patent No. 4841927
For example, there is a requirement to simultaneously receive a plurality of data output from an analog circuit at circuits existing at positions apart from one another in a semiconductor chip when a signal of the analog circuit is corrected by a digital circuit, or the like. To receive the plurality of data at the same timing, there is a method transmitting the plurality of data and a clock signal to a plurality of flip-flop circuits.
However, when a transmission distance becomes long, there is a possibility in which a skew between the data and the clock signal becomes large, and therefore, it is necessary to tighten a timing constraint as for all of the data and the clock signal when a transmission circuit is designed so as to satisfy a constraint for a setup/hold time enabling the flip-flop circuit to normally receive the data. Besides, when the skew is large, it is difficult to design at a required operating frequency.